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446
Account age
3 yrs
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🎁 Free analysisfor sylefeb
Known for
44 views
At FCCM 2026 I saw a keynote by Onur Mutlu on abusing DRAM chip timings to have them perform vector (row) copies and even or/and/nand computations on entire rows, 'for free' (happens physically through capacitors charge). And this is on current, off-the-shelves DDR3/DDR4 memory!
Well, I've got a bunch of great FPGA boards featuring good old SDRAM chips and ...
It turns out RowClone is possible on
11 views
Working on making PLLs easier to use in #Silice, here testing with a #ulx3s / ECP5 board. Four clocks of same frequency, phased out 90 degrees each. If you are wondering why the clock signals are not perfect ... check the wiring 😅 .
5 views
Here is the board, looking forward to explore all features!
2 views
This is the basic #Silice VGA test, somewhat of a tradition, I always start there when adding a new board. Who's new in this list ? Yes! Working on integrating the GateMate A1 evaluation board! Stay tuned for more info soon. #CologneChips #GateMate
📊 Post engagement
Recent posts · likes + reposts
Feb 17latest
12
Avg engagement / post
5–9
Typical post (engagement)
2.7%
Engagement vs followers
47/100
Variable reach
Nov 2022
On Mastodon since
Half of recent posts land between 5 and 9 likes + reposts (median 6) — reach is spiky, driven by the occasional post that pops.
🔥 Top post: At FCCM 2026 I saw a keynote by Onur Mutlu on abusing DRAM chip · 44 likes + reposts
📊 Activity & format
Posting cadence
0.67 / week
A lower-frequency account — each post lands with more weight.
Content mix
Mostly text
Recent: 8 text · 2 image · 2 video.
Follower / following
2.8×
Follows 157 back. A more reciprocal / networked account.
Recent posts
View on Mastodon ↗▶
🔥 Top post
At FCCM 2026 I saw a keynote by Onur Mutlu on abusing DRAM chip timings to have them perform vector (row) copies and even or/and/nand computations on entire rows, 'for free' (happens physically through capacitors charge). And this is on current, off-the-shelves DDR3/DDR4 memory!…
<rant> Growing tired of CMake deprecation breaking my builds just to increase a version number. Would be great if it would actually detect deprecated features ... anyway, going back to editing tens of CMakeLists.txt files. </rant>
For exploring this I built an SDRAM 'playground' controller SoC with a tiny RISCV CPU, in Silice (https://github.com/sylefeb/Silice , my HDL).
So far I could not get bitwise AND / OR / NAND to work but that's the next milestone!
All code i…
RE: https://graphics.social/@xavierchermain/116601717858757016
Our non-planar slicing technology is getting faster and more reliable. Forming partial layers before trajectories is a key factor in improving performance and printing quality.…
Working on making PLLs easier to use in #Silice, here testing with a #ulx3s / ECP5 board. Four clocks of same frequency, phased out 90 degrees each. If you are wondering why the clock signals are not perfect ... check the wiring 😅 .
Here is the board, looking forward to explore all features!
▶
This is the basic #Silice VGA test, somewhat of a tradition, I always start there when adding a new board. Who's new in this list ? Yes! Working on integrating the GateMate A1 evaluation board! Stay tuned for more info soon. #CologneChips …
5/5 A couple additional notes.
'WhyNot?' was done the last day before deadline during coffee breaks and at night (but starting from Warp). It has a couple egregious bugs I'll talk about in an upcoming write-up :).
Both designs are written…
4/5 So congratulations to everyone and thanks to #TinyTapeout for making all of this possible!! I would never have imagined doing a (winning) demoscene entry in 2026 on actual ASIC. This is beyond wild. Last I was involved in the demoscene…
3/5 All demos feature innovative approaches for graphics and music, with original design decisions. Also there is no 'small demo' here. Many entries are first time #Verilog design and certainly first time in #ASIC! Even the simplest displa…
2/5 It's amazing to win 1st place in these categories, but I want to outline how impressive and creative all the demos are. I worked on Warp in my little corner (during summer vacation, thinking on the beach, implementing under the stars :…
1/5 My two demos, Warp and WhyNot? won 1st place in 'Graphics' (Warp) and 1st place in 'Best for size' and 'Single tile' (WhyNot?) at the #TinyTapeout tt08 demo competition. Huge thanks to the jury for the recognition. This means a lot to …
Working on making PLLs easier to use in #Silice, here testing with a #ulx3s / ECP5 board. Four clocks of same frequency, phased out 90 degrees each. If you are wondering why the clock signals are not perfect ... check the wiring 😅 .
Here is the board, looking forward to explore all features!
▶
This is the basic #Silice VGA test, somewhat of a tradition, I always start there when adding a new board. Who's new in this list ? Yes! Working on integrating the GateMate A1 evaluation board! Stay tuned for more info soon. #CologneChips …
5/5 A couple additional notes.
'WhyNot?' was done the last day before deadline during coffee breaks and at night (but starting from Warp). It has a couple egregious bugs I'll talk about in an upcoming write-up :).
Both designs are written…
4/5 So congratulations to everyone and thanks to #TinyTapeout for making all of this possible!! I would never have imagined doing a (winning) demoscene entry in 2026 on actual ASIC. This is beyond wild. Last I was involved in the demoscene…
3/5 All demos feature innovative approaches for graphics and music, with original design decisions. Also there is no 'small demo' here. Many entries are first time #Verilog design and certainly first time in #ASIC! Even the simplest displa…
2/5 It's amazing to win 1st place in these categories, but I want to outline how impressive and creative all the demos are. I worked on Warp in my little corner (during summer vacation, thinking on the beach, implementing under the stars :…
1/5 My two demos, Warp and WhyNot? won 1st place in 'Graphics' (Warp) and 1st place in 'Best for size' and 'Single tile' (WhyNot?) at the #TinyTapeout tt08 demo competition. Huge thanks to the jury for the recognition. This means a lot to …
🐘 Community & instance
Home server
mastodon.online
A large general-interest Mastodon server. On the fediverse the server a creator picks hints at their community — this one spans all topics.
On Mastodon since
Nov 2022
Joined in the Twitter-exodus wave of late 2022 — part of the migration that made Mastodon a real destination.
💡 Facts
🗓️Joined Mastodon in 2022 — 3 years ago.
👁️Averages 12 views per post.
📤Posts about 0.7× per week.
🕵️ Fake follower check
Estimated66/100
Good
Credibility score
89%
Real
Real audience
Low
Fake-follower risk
High
Data confidence
- Est. 89% real, active audience · Low fake-follower risk.
- Engagement (~2.7% of followers engage each post) is around typical for Mastodon.
- Established account (3+ years old).
Heuristic estimate from engagement, follower ratios, account age & growth — a screening signal, not a guarantee.
About
Researcher, maker. Creator and lead developer of #IceSL and #Silice. Explores algorithms for #3dprinting, #fpga, #gpu, #procgen.
📸 Gallery
🔀 Audience overlap
EstimatedEstimated shared audience with similar creators — useful for avoiding overlap (or doubling down) when planning a campaign.
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