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Well this explains the interest in Zvdot4a8i
https://jia.je/software/2026/05/22/spec-cpu-2026-workload-analysis-int-rate-en/#2-1to6_nnue
https://github.com/riscv/riscv-isa-manual/pull/2576
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I tested the impact of disabling RVC on the SpacemiT X100 with clang.
Enabling RVC resulted in a roughly 10% performance improvement, which is higher than I expected.
AFAIK while the X100 supports a handful of fusion pairs, those aren't compressed only. (bitwise+bitwise, mul+add, add+load/store, slli+sr*i)
The fetch bandwidth is 16-byte / cycle, so enough to saturate the 4-way decode without RVC,
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🔥 Top post: Well this explains the interest in Zvdot4a8i https://jia.je/soft · 5 likes + reposts
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Well this explains the interest in Zvdot4a8i
https://jia.je/software/2026/05/22/spec-cpu-2026-workload-analysis-int-rate-en/#2-1to6_nnue
https://github.com/riscv/riscv-isa-manual/pull/2576
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"A Faster Multiplicative Inverse (Mod A Power Of 2)"
https://jeffhurchalla.com/2022/04/25/a-faster-multiplicative-inverse-mod-a-power-of-2/
RE: https://mastodon.gamedev.place/@zeux/116766307369651211
gf2p8affine mentioned
https://bitmath.blogspot.com/2026/06/what-is-absx-y.html "What is abs(x - y)"
A great blog post as usual.
But what if I want the shortest distance between two points on the 2d ring, so not around the ring.
I feel like overlapping FP and integer register file and ports may be better than overlapping FP with SIMD.
Because you kind of want scalar FP to be higher issue and lower latency that you need for SIMD float operations.
If you have 128-b…
Tenstorrent submitted the full rvv-bench results for Ascalon-X and Ascalon-S:
https://camel-cdr.github.io/rvv-bench-results/tt_asc_x/index.html
https://camel-cdr.github.io/rvv-bench-results/tt_asc_s/index.html
#riscv #rvv #simd
I tested the impact of disabling RVC on the SpacemiT X100 with clang.
Enabling RVC resulted in a roughly 10% performance improvement, which is higher than I expected.
AFAIK while the X100 supports a handful of fusion pairs, those aren't co…
My new favorite past time:
When somebody proposes a new RVV extension, fixing/optimizing their baseline RVV implementation.
John Hauser improvement:
psub.b a0,a0,t1 # t1 = eight '0's
pmulu.h.b00 t0,a0,t2 # t2 = 0x_000A_000A_000A_00A0
pmhaccsu.h.b1 t0,t3,a0 # t3 = 0x_0100_0100_0100_1000
pm4addu.h a0,t0,t4 # t4 = 0x_00…
RVP version:
psub.b a0, a0, t1='0'
mulw t0, a0, t2=10
mvm a0, t0, t3=~0xFF
pm4addu.b a0, a0, t4=0x010a6464
pm2addu.w a0, a0, t5=10000<<32|1
sadly there is no, pm2addu.b nor pmull.b, so it's one instruction more, than it should've been.
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