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Eee… LDA 12, STA &FEFF, INC &FEFF… sure enough it increments to 13. The CPU can read and write this memory-mapped register that directly drives the LEDs.
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Machinations.
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Well, that was way fiddlier than it needed to be but gosh darn it I think I've got the CPU working. It's pulling the reset vector at &FFFC-D, jumping correctly to &D123, doing LDA 12, STA &345, AND 00, LDA &345 (yes, the correct value is being read back in), then JMP (&FFFC) for an infinite loop. I
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Something like this, I hope. If I use Arlet’s 6502 core that plays nice with synchronous Block RAM, and break everything down into a clear pipeline. The key is to reload the shift register in cycle 10, ready in time for its first palette index and RGB output channels update in cycle 11, ready in tim
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🔥 Top post: Eee… LDA 12, STA &FEFF, INC &FEFF… sure enough it increments to · 2 likes + reposts
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Eee… LDA 12, STA &FEFF, INC &FEFF… sure enough it increments to 13. The CPU can read and write this memory-mapped register that directly drives the LEDs.
In VSCode, my 6502 assembly language script writes a value to 0hFEFF, which my Verilog memory-maps to a register that is in turn connected to the physical LEDs at the top level.
Was also a bit of a faff trying to force it to use the Block RAM instead of LUTs but I think it's sorted now.
EDIT: Tweaked the code so it's mutually exclusive read or write, which makes it NO_CHANGE rather than READ_FIRST and is a closer …
Well, that was way fiddlier than it needed to be but gosh darn it I think I've got the CPU working. It's pulling the reset vector at &FFFC-D, jumping correctly to &D123, doing LDA 12, STA &345, AND 00, LDA &345 (yes, the correct value is b…
Aha! The CPU appears to be pulling its reset vector. Which means it works. Next session I gotta try to un-bork the RAM.
Machinations.
Something like this, I hope. If I use Arlet’s 6502 core that plays nice with synchronous Block RAM, and break everything down into a clear pipeline. The key is to reload the shift register in cycle 10, ready in time for its first palette i…
Some nice ways of expanding 6-bit to 12-bit RGB.
I wonder if that’s it.
Summat like this would be handy, if I could do it.
Right, let's do this properly. Apparently these programmable logic devices prefer clock enable signals that are high only for the duration of a master clock cycle, because power, synchronisation, ease of synthesis etc. That's why I kept se…
I wonder what this is. Track inspection gizmotronics?
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